Fundamental Technologies Cassini MIMI Pages

Data Processing Unit

J. Dandouras, MIMI team meeting, October 1994

DPU Block Diagram.  (Click on figure for large version.)

• MIMI DPU Analog Electronics I/F Test
• MIMI DPU Turntable I/F Test
• Figures
• MIMI DPU BB Memory Board and MIMI DPU BB Processor Board
• MIMI DPU BB LEMMS - BIU I/F Board and MIMI DPU BB Test Board
• MIMI DPU BB - 2 views
• MIMI DPU BB Motherboard and MIMI DPU BB
• Flight Model Preliminary Parts List
• Preliminary Mass Estimate
• Preliminary Power Estimate
• MIMI DPU Schedule
• DPU Connectors
• DPU LEMMS Motor Interface
• ACTEL: Watchdog, Wait-State Generator
• Memory Map of EPU
• Memory Map of CPU
• EPU Interrupts
• CPU Interrupts
• ASIC Bus Address Decoder, Configuration and Status Registers, Bus Control Logic, and Interrupt Controller
• Synchronous Receiver Transmitter
• EPU Software Tasks (preliminary design), Normal Mode
• CPU Software Tasks (preliminary design), Normal Mode
• DPU Software Configuration
• DPU Software Schedule
• The MIMI LEMMS Turntable/DPU Interface

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Updated 6/17/08, T. Hunt-Ward
tizby@ftecs.com